I've read through the Stamp9G20 and Atmel AT91SAMG20 documentation and still find myself confused about pin multiplexing and the fact that some I/O pins are powered by VDDIOM and others by VDDIOP.
My understanding is that the Atmel processor's VDDIOM pin is powered by 1.8V on the Stamp9G20 and that all I/O pins for PIO C are powered by VDDIOM.
If this is the case, then as an example, how can I use all of the chip select pins for SPI1 when some of them are on PIO C (1.8V logic) and others are on PIO B (3.3V logic)? I suppose I would need voltage level translation on my application board?
Also, some of the SPI1 pins are multiplexed with the address bus (PC5/A24/SPI1_NPCS1). Is A24 used for addressing the SDRAM on the Stamp9G20? If so, then it seems this pin is not available for use by SPI1.
As another example, how can my design use the Ethernet MAC in MII mode and use the two-wire interface since the TWI pins are multiplexed with ETX2 and ETX3?
I understand the pin multiplexing is a function of the Atmel processor and not a design characteristic of the Stamp9G20, I just need some further explanation of how an application can use several peripherals when the I/O pins are all multiplexed.
Re: Stamp9G20 pin multiplexing and VDDIOM
My understanding is that the Atmel processor's VDDIOM pin is powered by 1.8V on the Stamp9G20 and that all I/O pins for PIO C are powered by VDDIOM.
If this is the case, then as an example, how can I use all of the chip select pins for SPI1 when some of them are on PIO C (1.8V logic) and others are on PIO B (3.3V logic)? I suppose I would need voltage level translation on my application board?
Yes, the pins have a high level of 1.8V and you would need level shifting, if you want to use 3.3V levels. Alternatively, you could use different pins as SPI chip select. The Linux drivers already toggle the pins manually as there were some bugs with the chip select on AT91 in the past, so it is really easy to use all GPIO pins as chip select. When registering your SPI chip selects in the board file, just specify the pin in the controller_data member of the spi_board_info struct (look into the different board files for examples on registering SPI chip selects).
Also, some of the SPI1 pins are multiplexed with the address bus (PC5/A24/SPI1_NPCS1). Is A24 used for addressing the SDRAM on the Stamp9G20? If so, then it seems this pin is not available for use by SPI1.
This pin is not used for addressing, but as already said, you don't have to use these pins.
As another example, how can my design use the Ethernet MAC in MII mode and use the two-wire interface since the TWI pins are multiplexed with ETX2 and ETX3?
If you really need MII mode, there is also a GPIO based alternative. Linux includes a I²C driver using only to GPIO pins. It actually works more correct and faster than the driver for the TWI controller (this also has to do with some bugs in earlier AT91 micro controller, which are now fixed, but the driver is not adjusted for the fixed controller). You can find the needed code to register the GPIO based driver in the file
arch/arm/mach-at91/at91sam9260_device.c. You have to put this code into the board file of the Stamp9G20 and adjust the pins as desired.