Hello,
i'm currently try to reduce the power consumption on the STAMP9G20. One and a very effective way is, to reduce the clock speed of the CPU and the peripherial components.
On my atmel Evalution Kit (AT91SAM9G20) i changed the bootstrap-bootloade-code to achieve a lower clock rate. I got this code for free from the atmel website. I tried to find the correspondig code for the Stamp9G20, but can't find it.
Can please tell me, if this code is for free and where I find it?
Thanks in advance.
Re: Clock and PLL initialisation in Bootstrap?
The bootstrap sources are on your Starterkit-CD. You need a stand-alone arm toolchain to compile it (like from CodeSourcery). Also bootstrap needs to be flashed via SAMBA.
For playing around, you can also set the PLL-registers in u-boot, but you have to change the baudrate register from the DBGU as well in one step, otherwise you loose your console.
Re: Clock and PLL initialisation in Bootstrap?
Thanks for your reply.
I can change the clock rate when i use mmap() in linux to write into the arm-register. But as you mentioned this changes the baudrate of the debug port too and the linux-delay-loop won't work as expected.
I only purchased the Stamp9G20, the StampAdaptor 2 and the Panel-Card Connector. So i did't recieve the CD. Is there another way then buying the CD to get the source code?
Thanks in advance
Re: Clock and PLL initialisation in Bootstrap?
Changing the clock rate in Linux is not such a good idea, because there are too many associated clocks, which do not adapt: SD/MMC, all UARTS, SPI and maybe more. Linux calculates the correct clocks on the frequency which it has on boot.
So changing the register in u-boot is not so problematic, just change the baudrate divisor and the PLL divider in one line.
I put the bootstrap sources in our download section here, it is roughly the same as for the Atmel-EK.
Re: Clock and PLL initialisation in Bootstrap?
Ok, thank you very much.
Re: Clock and PLL initialisation in Bootstrap?
Can you please give an "example line" for how to change the baudrate divisor and the PLL divider?